1. Field of the Invention
The present invention relates to power semiconductor devices, especially to MOS (metal-oxide-semiconductor) controlled bipolar device, including Insulated Gate Bipolar Transistor (IGBT).
2. Related Background Art
MOS (metal-oxide-semiconductor) controlled bipolar device is the preferred device for high power applications, capable of providing high blocking voltage and high conducting current and can be controlled conveniently by MOS (metal-oxide-semiconductor) gate. As a MOS controlled bipolar device, IGBT is the main-stream device for high power applications. There are many different IGBT structures with different performances. CSTBT structure has been proposed as an advanced IGBT structure. In the CSTBT structure, a relatively high concentration N-type CS (carrier stored) layer is formed under P-well, as disclosed in published conference paper (“Carrier Stored Trench-Gate Bipolar Transistor (CSTBT)—A Novel Power Device for High Voltage Application”, H. Takahashi, et al., the 8th International Symposium on Power Semiconductor Devices and ICs 1996, pp 349-352, IEEE). This way, carrier density in forward conduction mode is increased and collector-emitter saturation voltage (Vcesat) is decreased.
Plugged cell structure has been proposed for CSTBT. By adding plugged cells, miller capacitance can be reduced and short circuit current oscillation can be suppressed, as disclosed in U.S. Pat. No. 6,953,968 and U.S. Pat. No. 8,507,945 (which issued to Nakamura et al. on Oct. 11, 2005 and Aug. 13, 2013 respectively) which is incorporated herein by reference and is hereinafter referred to as the '968 patent and '945 patent respectively.
A typical CSTBT structure described in the '968 patent and '945 patent with plugged cells described above is shown in FIG. 1. This structure includes: metal collector layer 13 on backside, P-type collector layer 12, N-type field stop layer 11 and N-drift layer 10, which is a lightly doped N-type layer. There are active cells 40 and plugged cells 50 on top of the device. The active cell 40 and plugged cell 50 are separated by a trench 38. The gate trench structure 37 is formed of a polysilicon core 6 which is surrounded by a gate oxide layer 9. Polysilicon core 6 is connected to gate electrode 30. The trench structures 38 of plugged cells are formed by polysilicon core 3 which is surrounded by gate oxide layer 9. Polysilicon 3 and metal emitter layer 5 are both connected to the emitter electrode. Besides the trenches in both active cells and plugged cells, there are P-type wells 7a/7b and N-type CS layers 8. P-well 7b in plugged cells are not connected to any electrode, thus they are floating. Above P-well 7a in the active cell, there are N+ emitter layer 1, which is a heavily doped N-type layer, and P+ contact layer 2, which is a heavily doped P-type layer, and they are connected to metal emitter layer 5 through the opening 20 in the insulation layer 4.
In plugged cells of device structure shown in FIG. 1, a PN junction is formed between P-wells 7a/7b and N-type CS layers 8. Although P-wells 7b are floating, this PN junction still contains built-in depletion regions. These depletion regions reduce the stored carrier concentration in forward conduction mode, thus the Vcesat is relatively high.
To overcome the above mentioned problems, an improved plugged cell structure for CSTBT has been proposed, as disclosed in Chinese patent application No. 201410199352.4 (which is accepted on May 13, 2014) which is incorporated herein by reference and is hereinafter referred to as the '352.4 patent. The characteristics is that the P-wells in plugged cells are completely removed as shown in FIG. 2, thus the carrier density in forward conduction mode is further increased and collector-emitter saturation voltage (Vcesat) is further decreased. This structure comprises: metal collector layer 13 on the device backside, P-type collector layer 12, N-type field stop layer 11 and N-drift layer 10, which is a lightly doped N-type layer. There are active cells 40 and plugged cells 50 on top of the device. The active cell 40 and plugged cell 50 are separated by a trench 38. The gate trench structure 37 is formed of a polysilicon core 6 which is surrounded by a gate oxide layer 9. Polysilicon core 6 is connected to gate electrode 30. The trench structures 38 of plugged cells are formed by polysilicon core 3 which is surrounded by gate oxide layer 9. Polysilicon 3 and metal emitter layer 5 are both connected to emitter electrode. There are P-type wells 7 and N-type CS layers 8 in active cells. In plugged cells, there are N-type CS layers 8 but no P-type wells 7. Above P-well 7 in the active cell, there are N+ emitter layer 1, which is a heavily doped N-type layer, and P+ contact layer 2, which is a heavily doped P-type layer, and they are connected to metal emitter layer 5 through the opening 20 in the insulation layer 4.
In contrast to the Device in FIG. 1, the FIG. 2 device has a no floating P-wells 7b in the plugged cells, so built-in depletion regions between floating P-wells 7b and N-type CS layers 8 are removed, resulting in higher stored carrier concentration and a lower Vcesat. However, due to the lack of these built-in depletion regions, the recombination process of stored carrier is slowed down, therefore the turnoff process is also slowed down and turnoff energy is noticeably increased. Thus, the Vcesat of FIG. 2 structure is lower than that of FIG. 1 structure, but the turnoff energy of FIG. 2 structure is higher than that of FIG. 1 structure.
Therefore, what is needed is a new design of IGBT structure to achieve better performance tradeoff between Vcesat and turnoff energy.
The above and other objects, effects, features, and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings